1. Field of the Invention
This invention relates to the field of monostable multivibrators, and in particular monostable multivibrators used in circuits that require a controlled delay that is a fraction or multiple of a VCO period.
2. Background Art
Information is often transmitted in bit stream format. To accurately decode a serial bit stream, bit frames or bit windows must be accurately defined. A one-to-one correspondence exists between each bit and each frame or window. For a variety of reasons, data bit streams may include a degree of "jitter" which tends to force a data bit near or past a bit window boundary. To maximize the efficiency of data recovery in prior art, the average bit position is estimated and a decode window is defined having a nominal center coinciding with the average center bit position of the data stream. However, problems still exist when the jitter causes the bit position to extend over a window edge.
Prior art clock recovery circuits utilize phase locking via a phase locked loop (PLL) to generate one edge of a data window and utilize a quarter cell delay line to generate the other edge. In a clock recovery circuit, if the data stream does not consist of uniformly spaced pulses, the phase detector in the PLL generates a large signal error whenever a clock pulse occurs without a data pulse. To prevent this large error signal, a monostable multivibrator, or "one-shot", is implemented to disable the phase detector until a predetermined period before a data pulse. At this point, the one-shot enables the phase detector, and a phase comparison is made between the next data edge and the next clock edge. As soon as the comparison is finished, the phase detector is disabled.
Prior one-shots have been constructed using a combination of resistors and capacitors, and the one-shot period is a function of the RC time constants of the system. If implemented as an integrated circuit, process variations may affect the circuit timing. A typical integrated circuit process might have resistors with a .+-.10% tolerance and 1500 to 3000 ppm temperature coefficients, and capacitors with a .+-.10% tolerance and negligible temperature coefficients. Combined together, these tolerances and temperature coefficients can produce errors as large as 57% over a 100.degree. C. change in temperature. To attain high accuracy, the prior art uses external components. These external components are highly undesirable since, on an integrated circuit, this means another pin must be added.
Therefore, it is an object of the present invention to provide a controlled delay that is a precise fraction or multiple of a VCO period.
It is another object of the present invention to cancel the effects of the component variations on one-shot timing.